1. Field of the Invention
The present invention relates to a packet switch device for large-scale packet switching.
2. Description of the Related Art
With the explosive expansion of the Internet and with the advent of media handling large-amount or high-quality information, expectations have been running high in recent years for an improvement in a large-scale communications infrastructure that can flexibly handle a massive amount of data. Additionally, there has been a growing interest in a switch having a capacity of several hundreds of gigabytes to several terabytes, which is a key to actualization.
FIG. 1 exemplifies the configuration of a conventional input buffer switch.
In this configuration, a crossbar switch is a simple switch that is positioned at a stage succeeding input buffers, and that switches on/off each intersection point in a matrix generated when input and output HWs (highways) are arranged vertically and horizontally. At the exit of the input buffers, the crossbar switch can be configured not to include buffers. Namely, input packets are grouped into packets destined for output ports #1 through #N within the input buffers, and the grouped packets are stored. A scheduler outputs, for example, the packets to be output to the output port #1 at the appropriate timing so that they do not collide within the crossbar switch.
To expand the capacity of such a crossbar switch, a method connecting HWs in multiple stages in a matrix state, and a method bit-slicing one HW and arranging switches in parallel are considered as conventional techniques.
FIG. 2 shows a conventional crossbar switch expanding method, with which the capacity of a crossbar switch is expanded by connecting switches in multiple stages in a matrix state.
This figure shows the configuration which achieves its object by adding crossbar switches 11-1 through 11-3 in a matrix state when a single crossbar switch 10 which originally uses 4-input and 4-output lines is expanded to be a switch using 8-input and 8-output lines. In this configuration, the expansion method is simple. However, the number of crossbar switches is squared each time the capacity is expanded, leading to a very large hardware configuration.
FIG. 3 shows a conventional expansion method bit-slicing one HW, and arranging switches in parallel.
Assume that one M×M matrix switch is first arranged, and switching is made, for example, in units of 8-bit packets with the expansion method shown in FIG. 3. To expand this switch, an 8-bit packet is disassembled into 4-bit data, and switching is made by 2 M×M matrix switches, which respectively output the 4-bit data to the same output HW in parallel. Then, the output HW reassembles the 4-bit data into the 8-bit packet, and outputs the reassembled packet.
To further expand the capacity with the bit-slicing method shown in FIG. 3, one packet is further disassembled, and a required number of matrix switches are arranged. For instance, an 8-bit packet can be disassembled into 1-bit data. Therefore, this packet can be disassembled into 8 at the maximum. Accordingly, also 8 matrix switches are prepared, and each of the switches is made to switch 1-bit data. Bit data of one packet is output to the same output HW, which reassembles and transmits the 8-bit packet.
With the connections of crossbar switches in multiple stages shown in FIG. 2, the hardware amount increases with the requirements of IFs for expansion connections and with the square of the switch scale. Compared with this method, the bit slicing shown in FIG. 3 only requires the hardware proportional to the scale of a switch, thereby reducing a switch size. Note that, however, if the number of inputs/outputs of an HW accommodated by a switch is large, the number of input/output terminals proportional to that of the inputs/outputs is required with the bit slicing. Furthermore, a method attaching switch on-off information as the tag information of a packet to reduce the number of switch terminals is considered. However, the tag information must be attached to each bit with the bit slicing method, so that a process overhead becomes large.
FIG. 4 shows an example where a tag is attached to data with the bit slicing method.
If a packet having a payload composed of 63 words having 8-bit length is switched in units of packets, one tag may be attached to this packet. Namely, in FIG. 4, a tag composed of 1 word having 8-bit length is attached. If this packet is bit-sliced and disassembled into 1-bit data, it is necessary to attach a tag of 8 words having 1-bit length to each of the disassembled payloads of 63 words, and to switch each payload by an individual matrix switch. Accordingly, the data having 64 words when being switched in units of packets increases to 71 words if it is bit-sliced.
Furthermore, the following problems exist.                If a fault occurs in one slice, a packet itself is discarded (a complete packet cannot be transmitted), leading to system down.        Expansion cannot be made online.        